Current-source gate driver

ABSTRACT

Provided is a current-source gate driver for use with a switching device having a gate capacitance, including an input terminal for receiving a DC voltage; a first switch connected between the input terminal and an output terminal; a second switch connected between the output terminal and a circuit common; a series circuit comprising a first capacitor and an inductor, the series circuit connected between the input terminal and the output terminal; wherein the gate capacitance of the switching device is connected between the output terminal and the circuit common. The current-source gate driver improves efficiency of the power switching devices of a voltage regulator module or other switching converter.

RELATED APPLICATION

This application claims the benefit of the filing date of U.S.Provisional Patent Application Ser. No. 61/064,233, filed Feb. 22, 2008,the content of which is hereby incorporated by reference in itsentirety.

FIELD OF THE INVENTION

This invention relates to a gate driver for use in a voltage regulatormodule or other switching converter. In particular, this inventionrelates to a current-source gate driver for improving efficiency of eachof the power switching devices of a voltage regulator moduleindependently.

BACKGROUND OF THE INVENTION

To meet the strict transient requirements of future microprocessors andto reduce the number of passive components required to achieve highpower density, the switching frequency of voltage regulators (VR) willmove into the megahertz (MHz) range in the next few years [1]-[4].

However, an increase in switching frequency may lead to poor efficiencyof the VR due to excessive switching loss and gate drive loss, which areproportional to the switching frequency. Consequently, overallperformance of the VR will be degraded. More importantly, it has beenshown that in applications such as a high frequency (1 MHz) synchronousbuck VR, the parasitic inductance, especially the common sourceinductance, has a substantial propagation effect during the switchingtransition of the power switching devices and thus results in highswitching loss [5].

The resonant gate drive technique has received considerable attention asan approach to recovering gate energy lost in conventional gate drivers.In the approach taken by Chen et al. [6], the power MOSFET gate was notactively clamped high or low, which resulted in poor noise immunity. Yaoet al. proposed resonant drivers using a coupled inductor [7] or atransformer [8] that were able to drive two MOSFETs. However, theleakage inductance of these approaches becomes substantial at MHzfrequency. A full-bridge topology drive circuit with one inductor todrive two ground-sharing MOSFETs in a 1 MHz Boost converter was proposedby Li et al. [9]. Dwane et al. [10] provided an assessment of resonantdrive techniques for use in low power dc/dc converters, and Lopez et al.[11] constructed a mathematical model to estimate the power loss of aresonant drive circuit. However, all of these approaches focus on gateenergy savings realized by the resonant gate driver, but do not considerthe potential switching loss savings, which are more important in a VRand other switching converters operating at MHz frequencies.

In our previous work [12]-[16], we showed that use of a constant drivecurrent in a resonant gate driver can significantly reduce the switchingtransition time and switching loss of power switching devices. Using acurrent-source topology for the driver in a buck VR, we demonstrated asignificant improvement in efficiency over the conventional voltagedriver at a switching frequency of 1 MHz. However, with that approach itwas not possible to achieve control of the power switching devicesindependently.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided acurrent-source gate drive circuit for use with a switching device havinga gate capacitance, comprising: an input terminal for receiving a DCvoltage; a first switch connected between the input terminal and anoutput terminal; a second switch connected between the output terminaland a circuit common; a series circuit comprising a first capacitor andan inductor, the series circuit connected between the input terminal andthe output terminal; wherein the gate capacitance of the switchingdevice is connected between the output terminal and the circuit common.

The current-source gate driver may further comprise a second capacitorconnected between a node between the first capacitor and the inductor,and the circuit common.

The current-source gate drive circuit may further comprise a thirdcapacitor connected between the node and the inductor.

The switching device may be a synchronous power switching device of abuck converter, or a low side power switching device of a bridge leg.

A second aspect of the invention relates to a current-source gate drivecircuit for use with a switching device having a gate capacitance,comprising: an input terminal for receiving a DC voltage; a rectifierconnected between the input terminal and a first node; a first switchconnected between the first node and an output terminal; a second switchconnected between the output terminal and a floating point; a seriescircuit comprising a first capacitor and an inductor, the series circuitconnected between the first node and the output terminal; and a secondcapacitor connected between the first node the floating point; whereinthe gate capacitance of the switching device is connected between theoutput terminal and the floating point.

In one embodiment, the series circuit may be connected between thefloating point and the output terminal.

The switching device may be a control power switching device of a buckconverter.

The switching device may be a high side power switching device of abridge leg.

A third aspect of the invention relates to a current-source gate drivecircuit for use with a switching device having a gate capacitance,comprising: an input terminal for receiving a DC voltage; a rectifierconnected between the input terminal and a first node; a first switchconnected between the first node and an output terminal; a second switchconnected between the output terminal and a floating point; a seriescircuit comprising a first capacitor and second capacitor, the seriescircuit connected between the first node and the floating point; and aninductor connected between a point between the first and secondcapacitors and the output terminal; wherein the gate capacitance of theswitching device is connected between the output terminal and thefloating point.

The current-source gate drive circuit may further comprise a thirdcapacitor connected in series with the inductor, between the first andsecond capacitors and the output terminal.

The switching device may be a control power switching device of a buckconverter.

The switching device may be a high side power switching device of abridge leg.

A fourth aspect of the invention relates to a voltage regulator having ahigh side power switching device and a low side power switching device,each said power switching device having a gate capacitance, comprising:the current-source gate drive circuit of the first aspect, above, fordriving the high side power switching device; and the current-sourcegate drive circuit of the second aspect, above, for driving the low sidepower switching device.

The inductor of the current-source gate drive circuit for driving thehigh side power switching device may share a magnetic component with theinductor of the current-source gate drive circuit for driving the lowside power switching device.

A fifth aspect of the invention relates to a method of controllingswitching of a switching device having a gate capacitance, comprising:

(a) providing a constant current source in a first direction to chargethe gate capacitance of the switching device;

(b) clamping the voltage across the gate capacitance to a high value, toturn the switching device on;

(c) reversing direction of the constant current source to discharge thegate capacitance of the switching device; and

(d) clamping the voltage across the gate capacitance to a low value, toturn the switching device off;

wherein the constant current source comprises an inductor current.

The switching device may be the high side power switching device or thelow side power switching device of a voltage regulator or a bridge leg.

A sixth aspect of the invention relates to a method of controllingindependently the switching of high side and low side power switchingdevices of a voltage regulator, each said power switching device havinga gate capacitance, comprising: independently applying the above methodto each of the high side and low side power switching devices of thevoltage regulator.

In one embodiment, inductor currents applied to the high side and lowside power switching devices are not equal.

Another embodiment may comprise applying the above method to the highside power switching device of the voltage regulator using a highinductor current; and applying the above method to the low side powerswitching device of the voltage regulator using a low inductor current.

The voltage regulator may be a buck converter.

In one embodiment, controlling may include repeating steps (a) to (d)once per cycle at a frequency of at least 300 kHz.

In another embodiment, the frequency is at least 1 MHz.

In the above embodiments, the switching device may be a power switchingdevice selected from a MOSFET (metal oxide semiconductor field effecttransistor), an IGBT (insulated gate bipolar transistor), and a MCT (MOScontrolled thyristor).

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described below, by way of example,with reference to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a generalized current-source gate drivecircuit of the invention;

FIG. 2 is a timing diagram showing key waveforms of the circuit of FIG.1;

FIGS. 3A-3D show equivalent circuits of the circuit of FIG. 1 for eachof four switching modes during one complete switching cycle;

FIGS. 4A and 4B are schematic diagrams of alternative embodiments of thecurrent-source gate drive circuit, suitable for driving aground-referenced power switching device;

FIGS. 5A to 5D are schematic diagrams of alternative embodiments of thecurrent-source gate drive circuit, suitable for driving a non-groundreferenced power switching device;

FIG. 6 is a schematic diagram showing the current-source gate drivecircuit used to drive two power switching devices in a bridge leg;

FIG. 7 is a schematic diagram showing two current-source gate drivecircuits used to drive the control and synchronous MOSFETs of a buck VRaccording to an embodiment of the invention;

FIG. 8 is a timing diagram showing key waveforms of the current-sourcegate drive circuits and MOSFETS of FIG. 7;

FIGS. 9A-9F show equivalent circuits of the circuit of FIG. 7 for eachof six switching modes during one complete switching cycle;

FIG. 10 is a plot showing optimization curves for a current-source gatedriver for the synchronous rectifier MOSFET of a buck converter;

FIG. 11 is a schematic diagram showing two current-source gate drivercircuits with an integrated inductor;

FIG. 12 is a diagram showing an integrated inductor structure suitablefor the integrated inductor of FIG. 11;

FIG. 13 is a plot showing the flux ripple cancellation effect of anintegrated inductor;

FIG. 14 is a trace showing gate signals for the control and synchronousMOSFETs of a buck converter built using the current-source gate drivecircuit of FIG. 7;

FIG. 15 shows traces of the inductor current waveforms of a buckconverter built using the current-source gate drive circuit of FIG. 7,with two discrete inductors;

FIG. 16 shows traces of the inductor current waveforms of a buckconverter built using the current-source gate drive circuit of FIG. 7,with an integrated inductor;

FIG. 17 is a plot comparing the efficiency of a buck converter having aconventional driver, a current-source gate driver with two discreteinductors, and a current-source gate driver having an integratedinductor;

FIG. 18 is a plot comparing the power loss of a buck converter having aconventional driver to that of a buck converter having a current-sourcegate driver with two discrete inductors, for an output of 1.5 V and 30A;

FIG. 19 is a plot comparing efficiency of a buck converter having acurrent-source gate driver with two discrete inductors, at outputvoltages of 1.0 V, 1.2 V, 1.3 V, and 1.5 V;

FIG. 20 is a schematic diagram of a hybrid current-source gate drivecircuit for driving the control power switching device of a buck voltageregulator, according to another embodiment of the invention;

FIG. 21 shows key waveforms of the circuit of FIG. 20;

FIGS. 22A and 22B are schematic diagrams of equivalent circuits of thecircuit of FIG. 20;

FIG. 23 shows traces of the gate signals and the inductor current of thecircuit of FIG. 20;

FIG. 24 shows traces of the voltage driver and current-source driversignals, and the inductor current of FIG. 20, for one cycle; and

FIG. 25 is a plot comparing the efficiency of the circuit of FIG. 20 andof a buck converter with conventional gate drivers.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

For the purpose of this description, the term MOSFET (metal oxidesemiconductor field effect transistor) will be used as a non-limitingexample for all switching devices, including power switching devices. Itwill be understood that other suitable devices, such as, for example, anIGBT (insulated gate bipolar transistor), or a MCT (MOS controlledthyristor), may be used for the power switching device. It will also beunderstood that other devices, such as a BJT (bipolar junctiontransistor, in which case a body diode (i.e., antiparallel diode) isrequired) may also be used for a drive switch of the current-source gatedriver.

As known in the art, a switching device such as a FET has inherentcapacitance. For example, for a FET, there is inherent capacitancebetween the gate terminal and the source terminal, between the drainterminal and source terminal, and between gate terminal and drainterminal.

As used herein, the terms “C_(gs)”, “gate capacitance”, “gatecapacitor”, “input capacitance”, and “input capacitor” areinterchangeable and refer to the inherent capacitance between the gateand source terminals of a FET switching device. Those of ordinary skillin the art will understand that the gate capacitance of a switchingdevice is distinct from and does not include any discrete capacitor thatmay be connected to the gate of the switching device. Expressions suchas “connected to the gate capacitance” and “connected to the gatecapacitor” refer to a connection to the gate or control terminal of suchswitching devices.

As used herein, the terms “C_(ds)”, “drain capacitance”, “draincapacitor”, “output capacitance”, and “output capacitor” areinterchangeable and refer to the inherent capacitance between the drainand source terminals of a FET switching device. Those of ordinary skillin the art will understand that the drain capacitance of a switchingdevice is distinct from and does not include any discrete capacitor thatmay be connected to the drain of the switching device. Expressions suchas “connected to the drain capacitance” and “connected to the draincapacitor” refer to a connection to the drain terminal of such switchingdevices.

As used herein, the term “C_(gd)” refers to the inherent capacitancebetween the gate and drain terminals of a FET switching device. Those ofordinary skill in the art will understand that the inherent capacitancebetween the gate and drain terminals of a FET switching device includesthe “Miller capacitor” or “Miller capacitance” of the device, which isrelated to the gain of the device. The terms “C_(gd)”, “Millercapacitor”, and “Miller capacitance” may be used interchangeably herein.Those of ordinary skill in the art will also understand that the C_(gd)of a switching device is distinct from and does not include any discretecapacitor that may be connected to the drain or gate of the switchingdevice.

As used herein, the term “current-source” is intended to refer to anidealized current-source which may be approximated by at least a portionof the magnetizing current of a transformer winding, a current throughan inductor, or the like. In embodiments of the current-source gatedriver described herein, the time constant of the inductor and theequivalent capacitor (e.g., the sum of C_(gs) and C_(gd)) of the powerswitching device is much larger (for example, 10 to 20 times larger)than the switching transition time (i.e., turn on time or turn off time)of the power switching device. With this condition, the inductor currentdoes not change substantially during the switching transition timeperiod. For example, any change in the inductor current may be less than20% of the maximum inductor current during the switching transitiontime. In contrast, the time constant of the inductor and the equivalentgate capacitor in a resonant gate drive circuit is of the same order asthe switching transition time. With this condition, the inductor currentwill change substantially (such as from zero to its maximum value)during the switching transition time.

In one aspect, the invention relates to an efficient current-source gatedrive circuit for high frequency (i.e., ≧1 MHz) applications. The drivecircuit uses a constant inductor current to achieve fast charging anddischarging of the input capacitor of the power switching device, whichleads to significant reduction of the switching time and the switchingloss. The current-source gate drive circuit returns energy to the supplyvoltage during intervals after the power switching device is turned onand after it is turned off.

It will of course be appreciated that the current-source gate drivecircuits described herein may be used at frequencies below 1 MHz, suchas, for example, 300 kHz to 1 MHz. As such, the current-source gatedrive circuit may be used at VR operating frequencies typical of currentVR designs (e.g., in the hundreds of kHz). Further, the upper limit ofthe operating frequency of the current-source gate drive circuitsdescribed herein may be determined by what is possible with currentlyavailable technology (e.g., up to 5 MHz), and is expected to increase ashigh frequency technology improves.

As will be described below, embodiments of the invention includecurrent-source gate drive circuits for driving the low side (i.e.,synchronous) power switching device and the high-side non-groundreferenced (i.e., control) power switching device of a buck converter,also referred to herein as a buck VR module. Moreover, the driveswitches of the gate drive circuits achieve zero-voltage-switching (ZVS)with near zero switching loss at very high frequency (i.e., ≧1 MHz).

In one embodiment, the current-source gate drive circuit is configuredfor use with a synchronous buck converter. The gate drive circuitprovides a high inductor current to achieve fast switching speed andreduce the switching loss for the high side (control) MOSFET, andprovides a lower inductor current to achieve high efficiency of the gateenergy recovery for the low side (synchronous) MOSFET. An additionalbenefit of fast switching speed of the power MOSETs is that the deadtime between the control MOSFET and synchronous MOSFET is reduced, whichreduces significantly both the body diode conduction loss and thereverse recovery loss.

In another embodiment the current-source gate driver includes adaptivevoltage control, to improve light load efficiency. Under light loadconditions, switching loss of a power MOSFET decreases greatly due tothe lower load current, and therefore it is not necessary to drive theMOSFET with high drive current. Indeed, under light load conditions, theportion of the total power loss (i.e., the power loss of the VR plus thecurrent-source gate driver) that is attributed to the current-sourcegate driver itself becomes greater. Because the power loss of thecurrent-source gate driver depends on its supply voltage, one option isto reduce the supply voltage of the current-source driver circuit toreduce its power loss, and thereby reduce the total power loss underlight load conditions. Therefore, in this embodiment, the supply voltageof the current-source gate driver is reduced according to the reductionof the load current, which leads to a reduction of the circulatingcurrent and of the resistive loss in the gate drive circuit to improvelight load efficiency. Suitable methods to reduce the supply voltageinclude, for example, a low drop out linear regulator, a charge pumpcircuit, or a small DC-DC converter. A supply voltage of, for example12V, may be reduced to a desired value, such as 8 V, or 5 V.

Another embodiment relates to a current-source gate driver with only onemagnetic component, which may be made by integrating two inductors, toreduce the magnetic core number. Such an embodiment is well suited foruse with a synchronous buck VR, and particularly for multiphaseinterleaved buck VRs, to reduce the complexity and cost of the VRcircuit.

1.A. Current-Source Gate Drive Circuit

FIG. 1 shows an embodiment of the current-source gate drive circuit. Itincludes two drive switches S₁ and S₂, an inductor L_(r), and a blockingcapacitor C_(b). Each drive switch S₁ and S₂ has a body diode, D₁ andD₂, respectively, and a drain capacitance C_(ds1) and C_(ds2),respectively. It will be understood by those of ordinary skill in theart that the body diodes and the drain capacitors are intrinsic orinherent to the switches S₁ and S₂, and are not discrete components. Vcis the drive voltage. Q is the power switching device (e.g., a MOSFET)and C_(gs) is the gate capacitance of the MOSFET. S₁ and S₂ arecomplementarily controlled.

1.B. Principle of Operation

FIG. 2 shows the key waveforms of the current-source drive circuit ofFIG. 1. There are four switching modes in a one switching cycle and theequivalent circuits are shown in FIGS. 3A-3D.

1) Mode 1 [t₀, t₁] (FIG. 3A): Prior to t₀, S₂ conducts and the inductorcurrent i_(Lr) increases in the positive direction. At t₀, S₂ is turnedoff. The inductor current i_(Lr) charges the drain capacitor C_(ds2) ofS₂ and the gate capacitor C_(gs) of the MOSFET Q and discharges thedrain capacitor C_(ds1) of S₁ simultaneously. The inductor peak currentI_(Lr) _(—) _(pk) can be regarded as a constant current-source during[t₀, t₁], which ensures very fast charging speed of the Miller capacitorof Q. Due to C_(ds1) and C_(ds2), S₂ is at zero-voltage turn-off. Thevoltage of C_(ds2), v_(c2), rises linearly and the voltage of C_(ds1),v_(c1), decays linearly.

2) Mode 2 [t₁, t₂] (FIG. 3B): At t₁, v_(c2) rises to V_(c) and v_(c1)decays to zero. The body diode D₁ conducts and S₁ is turned on withzero-voltage condition. The gate-to-source voltage of Q is clamped tothe drive voltage V_(c) through S₁. From t₁, the inductor current i_(Lr)decreases from the positive direction and then increases in the negativedirection.

3) Mode 3 [t₂, t₃] (FIG. 3C): At t₂, S₁ is turned off. i_(Lr) chargesthe drain capacitor C_(ds1) of S₁ and discharges the drain capacitorC_(ds2) of S₂ and the gate capacitor C_(gs) of the MOSFET Qsimultaneously. Due to C_(ds1) and C_(ds2), S₁ is at zero-voltageturn-off. The voltage of C_(ds1) rises linearly and the voltage ofC_(ds2) decays linearly.

4) Mode 4 [t₃, t₄] (FIG. 3D): At t₃, v_(c1) rises to V_(c) and v_(c2)decays to zero. The body diode D₂ conducts and S₂ is turned on withzero-voltage condition. The gate-to-source voltage of Q is clamped toground through S₂.

1C. Features of the Current-Source Gate Drive Circuit

A portion of the power MOSFET gate energy may be recovered.

The driver achieves quick turn-on and turn-off of the power switchingdevice, which reduces the switching loss of the power switching devicesignificantly.

The driver uses a current source to drive the power switching device andreduces the negative impact of parasitic inductance, especially thecommon source inductance, at high frequency. It is noted that in aconventional VR, the propagation effect due to parasitic inductanceduring the switching transition results in very high switching loss athigh frequency.

The drive switches S₁ and S₂ achieve ZVS operation, which leads to lowswitching loss at high frequency.

High noise immunity and alleviation of the dv/dt effect. The powerswitching device (e.g., MOSFET) gate is actively clamped high by S₁ andlow by S₂, eliminating false triggering due to noise spikes.

The current-source drive circuit has simple structure and a lowcomponent count, which makes it suitable for integration into a gatedrive IC chip. The complementary control scheme is also very simple.

2. Further Embodiments of the Current-Source Gate Drive Circuit

FIG. 4A and FIG. 4B show two further embodiments of the current-sourcegate drive circuit of FIG. 1. These circuits have the same features ofthe circuit of FIG. 1, and are based on the same principle of operationand have the same equivalent circuit. However, the embodiment of FIG. 1requires fewer components. In FIGS. 4A and 4B, the body diodes D₁ andD₂, and drain capacitors C_(ds1) and C_(ds2) of each drive switch S₁ andS₂ are shown as in FIG. 1, but are not labelled. C₁ and C₂ form acapacitor divider to block the DC offset voltage over the inductor.These circuits are suitable for driving a ground-referenced powerswitching device, such as, for example, the low side (synchronous)MOSFET of a buck converter.

FIG. 5A shows an embodiment of the current-source gate drive circuitsuitable for driving a non-ground referenced MOSFET such as, forexample, the high side (control) MOSFET of a buck VR. The current-sourcegate driver includes a bootstrap circuit with a diode D_(f) and flyingcapacitor C_(f). In FIGS. 5A to 5D, the body diodes D₁ and D₂, and draincapacitors C_(ds1) and C_(ds2) of each drive switch S₁ and S₂ are shownas in FIG. 1, but are not labelled. FIGS. 5B, 5C, and 5D show furtherembodiments of the high side driver topology.

The current-source gate drive circuit may also be used to drive twoMOSFETs in a leg of a half-bridge topology or a full-bridge topology toachieve the switching loss reduction and gate energy savings, as shownin FIG. 6.

3.A. Current-Source Gate Drive Circuit for a Synchronous Buck Converter

A synchronous buck converter is the most popular VR topology used today.In a high frequency synchronous buck converter, the high-side switch(control MOSFET) exhibits very high switching loss due to the commonsource inductance, and the low side switch (synchronous MOSFET) exhibitshigh gate drive loss. The high current of the current-source drivecircuits described herein achieves fast switching speed and reduces theswitching loss significantly, but high current increases the circulatingloss in the drive and reduces the efficiency of the gate energyrecovery. To maximize the total loss savings, different currents may beused for the control MOSFET and the synchronous MOSFET.

Thus, one embodiment of the current-source gate driver described hereinprovides independent drive for the control MOSFET and the synchronousMOSFET in a buck VR. For the control MOSFET, this involves a tradeoffbetween switching loss reduction and drive circuit loss; while for thesynchronous MOSFET, this involves a tradeoff between body diodeconduction loss and drive circuit loss. Moreover, the gate drive currentshould not flow through the power MOSFET.

All the above features may be achieved by the circuit shown in FIG. 7,which includes a synchronous buck converter with current-source gatedrive circuits for the control and synchronous MOSFETs. In thisembodiment, current-source driver #1 (CSD#1) provides a high inductorcurrent to achieve fast switching speed and reduce the switching lossfor the control MOSFET, and current-source driver #2 (CSD#2) provides alower inductor current to achieve high efficiency of the gate energyrecovery for the synchronous MOSFET. In the buck converter of FIG. 7, Q₁is the control MOSFET and Q₂ is the synchronous MOSFET. C_(gs1) andC_(gs2) are the inherent gate capacitances of Q₁ and Q₂ respectively.Current-source driver #1 and current-source driver #2 each have ahalf-bridge topology, consisting of drive switches S₁ and S₂, and S₃ andS₄, respectively. Current-source drivers #1 and #2 may be as shown inFIG. 7, or current-source driver #2 may be any one of the low-sidedrivers of FIG. 4A or 4B, and current-source driver #1 may be any one ofthe high-side drivers in FIG. 5A to 5D. With asymmetrical control, allthe drive switches may achieve zero-voltage-switching (ZVS). CSD#1 mayalso be regarded as a level-shift version of CSD#2. V_(c1) and V_(c2)are the drive voltages, which may be the same or different voltage. Thediode D_(f) provides the path to charge C_(f) to the voltage of thedrive voltage V_(c2). C_(b1) and C_(b2) are the blocking capacitors. S₁and S₂ are switched out of phase with complimentary control to drive Q₁,while S₃ and S₄ are switched out of phase with complimentary control todrive Q₂.

The key waveforms for the circuit of FIG. 7 are shown in FIG. 8. Theswitching transitions of charging and discharging C_(gs1) and C_(gs2)are during the interval of [t₀, t₂] and [t₃, t₅]. The peak currentsi_(G) _(—) _(Q1) and i_(G) _(—) _(Q2) during [t₀, t₂] and [t₃, t₅] areconstant during switching transition as seen in FIG. 8, which ensurefast charging and discharging of the gate capacitor and the gate todrain capacitor of Q₁.

The crossover level of the two gate signals is less than the thresholdvoltage of the switches so that the dead time may be minimized andshoot-through may also be avoided. This circuit has the features listedabove in section 1C, and in addition, the reduced switching timeprovided by the current-source gate drivers also helps to reduce thedead time between the control MOSFET and synchronous MOSFET, and alsoreduces the conduction loss and the reverse recovery loss of the bodydiodes.

The current-source gate drivers described herein have excellent dynamicresponse. When the duty cycle has a step change during a transient, bothof the current-source gate drivers may operate like conventional driversregardless of the blocking capacitors and the inductors. Moreover,during the transient, the current-source driver for the synchronousMOSFET may be shut down by turning on S₄ and clamping the gate of thesynchronous MOSFET to ground, which helps the VR have better dynamicresponse, due to the high forward voltage of the body diode of thesynchronous MOSFET when a step-down load happens.

In burst-mode control of a VR under very light load conditions withvariable frequency control, the current-source gate drivers may alsooperate similar to a conventional driver, except that a very smallamount of the energy stored in the inductor will be dissipated on theresistance of the drive circuit. But since the dissipated energy is verysmall and the switching frequency is much lower under burst-modecontrol, the efficiency of the VR will not be substantially affected.Furthermore, the following methods may be employed to improve the lightload efficiency: 1) reduce drive voltage of the control MOSFET to reducethe resistive loss of the circulating current and improve the recoveryefficiency of the gate energy; and/or 2) shut down the synchronousMOSFET to eliminate its gate drive loss.

3.B. Principle of Operation

The principle of operation of the circuit of FIG. 7 will be describedwith reference to FIG. 8. There are six switching modes in a switchingcycle and the equivalent circuits are given in FIGS. 9A-9F. D₁-D₄ arethe body diodes and C_(ds1)-C_(ds4) are the intrinsic drain capacitancesof drive switches S₁-S₄ respectively.

1) Mode 1 [t₀, t₁] (FIG. 9A): Prior to t₀, S₂ and S₃ conduct and theinductor current i_(Lr1) increases in the positive direction whilei_(Lr2) increases in the negative direction. Q₂ is on. At to, S₃ turnsoff. i_(Lr2) charges C_(ds3) and discharges C_(ds4) plus the inputcapacitor C_(gs2) simultaneously. Due to C_(ds3) and C_(ds4), S₃ is atzero-voltage turn-off. The voltage of C_(ds2) rises linearly and thevoltage of C_(ds4) decays linearly.

2) Mode 2 [t₁, t₂] (FIG. 9B): At t₁, v_(c3) rises to V_(c1) and v_(c4)decays to zero. The body diode D₄ conducts and S₄ turns on underzero-voltage condition. The gate-to-source voltage of Q₂ is clamped toground through S₄. At t₁, S₂ turns off. i_(Lr1) charges C_(ds2) plus theinput capacitor C_(gs1) and discharges C_(ds1) simultaneously. Due toC_(ds1) and C_(ds2), S₂ is at zero-voltage turn-off. The voltage ofC_(ds2) rises linearly and the voltage of C_(ds1) decays linearly.

3) Mode 3 [t₂, t₃] (FIG. 9C): At t₂, V_(c2) rises to V_(c2) and v_(c1)decays to zero. The body diode D₁ conducts and S₁ turns on underzero-voltage condition. The gate-to-source voltage of Q₁ is clamped toV_(c2) through S₁. i_(Lr1) and i_(Lr2) both decrease.

4) Mode 4 [t₃, t₄] (FIG. 9D): Before t₃, i_(Lr1) and i_(Lr1) changedpolarity respectively. At t₃, S₄ and S₁ turns off. i_(Lr2) chargesC_(ds4) plus C_(gs2) and discharges C_(ds3) simultaneously. Due toC_(ds3) and C_(ds4), S₄ is at zero-voltage turn-off. The voltage ofC_(ds4) rises linearly and the voltage of C_(ds3) decays linearly.i_(Lr1) charges C_(ds1) and discharges C_(ds3) plus C_(gs2)simultaneously. Due to C_(ds1) and C_(ds2), S₁ is at zero-voltageturn-off.

5) Mode 5 [t₄, t₅] (FIG. 9E): At t₄, v_(c1) rises to V_(c2) and V_(c2)decays to zero. The body diode D₂ conducts and S₂ turns on underzero-voltage condition. The gate-to-source voltage of Q₁ is clamped tozero through S₂.

6) Mode 6 [t₅, t₆] (FIG. 9F): At t₅, V_(c4) rises to V_(c1) and V_(c3)decays to zero. The body diode D₃ conducts and S₃ turns on underzero-voltage condition. The gate-to-source voltage of Q₂ is clamped toV_(c1) through S₃.

3. C. Current-Source Gate Drive Circuit Loss Analysis

The two current-source drivers (#1 and #2) have similar drive lossesexcept for different peak inductor currents. For each of them, the driveloss includes: 1) the resistive loss and gate drive loss of driveswitches (S₁-S₄); 2) the loss of the inductor (L_(r1) and L_(r2)); and3) the resistive loss caused by the internal gate mesh resistance of thepower MOSFETs.

From the volt-second balance condition across the inductor, the DCvoltage v_(cb) across the blocking capacitor C_(b) is derived asEquation (I)

v _(Cb)=(1−D)·V _(c)  (1)

where D is the duty cycle of S₁ and V_(c) is the drive voltage.

The relationship of the inductor value L_(r) and the peak inductorcurrent I_(Lr) _(—) _(pk) is given by Equation (2)

$\begin{matrix}{L_{r} = \frac{V_{c} \cdot D \cdot \left( {1 - D} \right)}{2 \cdot I_{{Lr}\; \_ \; p\; k} \cdot f_{s}}} & (2)\end{matrix}$

where D is the duty cycle of S₁, V_(c) is the drive voltage and f_(s) isthe switching frequency. By choosing the proper peak inductor current(drive current for the MOSFET), the inductor value can be obtained byEquation (2).

The inductor current waveform indicated in FIG. 8 may be regarded as atriangular waveform since the charging/discharging time [t₀, t₂] and[t₃, t₅] are very small and can be neglected. Therefore, the RMS valueof the inductor current I_(Lr) _(—) _(RMS) is I_(Lr) _(—) _(pk)/√{squareroot over (3)}.

Take driver #1 as an example. The RMS currents flowing through theswitches S₁ and S₄ can be derived as

$\begin{matrix}{I_{s\; 1\_ \; R\; {MS}} = {I_{{Lr}\; \_ \; p\; k\; 1} \cdot \sqrt{\frac{D}{3}}}} & (3)\end{matrix}$

The RMS currents flowing through switch S₂ is

$\begin{matrix}{I_{s\; 2\; \_ \; R\; {MS}} = {I_{{Lr}\; \_ \; p\; k\; 1} \cdot \sqrt{\frac{1 - D}{3}}}} & (4)\end{matrix}$

The conduction loss of S₁ and S₂ is expressed as

P _(cond) =I _(s1) _(—) _(RMS) ² ·R _(ds(on)) +I _(s2) _(—) _(RMS) ² ·R_(ds(on))  (5)

Substituting (3) and (4) into (5) yields

$\begin{matrix}{P_{{cond}\;} = {\frac{1}{3} \cdot I_{L\; r\; \_ \; p\; k\; 1}^{2} \cdot R_{{ds}{({on})}}}} & (6)\end{matrix}$

The copper loss of the inductor winding is expressed as

P _(copper) =R _(ac) ·I ² _(Lr) _(—) _(RMS1)  (7)

where R_(ac) is the AC resistance of the inductor winding. I_(Lr) _(—)_(RMS1) is the RMS value of the inductor current. Core loss of theinductor should be also included. The total inductor loss is given inEquation (8):

P _(ind) =P _(copper) +P _(core)  (8)

Both the charge and discharge currents flow through the internal gatemesh resistance RG of the power MOSFET and cause resistive loss. Thecharge and discharge current is the peak value of the inductor current.Thus the total loss caused by the internal resistance of the powerMOSFET Q₁ during turn-on (t_(on1)) and turn-off (t_(off1)) is expressedas

P _(RG) =R _(G1) I ² _(Lr) _(—) _(pk1)·(t _(on1) +t _(off1))·f _(s)  (9)

where R_(G1) is the internal gate resistor of Q₁ and f_(s) is theswitching frequency.

The gate drive loss of S₁ and S₂ is expressed as

P _(gate)=2·Q _(g) _(—) _(s) ·V _(gs) _(—) _(s) ·f _(s)  (10)

where Q_(g) _(—) _(s) is the total gate charge of a drive switch andV_(gs) _(—) _(s) is the drive voltage, which is typically 5V.

In conclusion, the total loss of current-source drive circuit of #1 isexpressed as

P _(Drive) =P _(cond) +P _(gate) +P _(ind) +P _(RG)  (11)

3.D. Design of a Current-Source Gate Drive Circuit for a Buck Converter

One feature of the current-source gate drive circuit is that it candrive the control MOSFET and the synchronous MOSFET independently withdifferent gate drive currents.

For the control MOSFET Q₁, this involves a tradeoff between theswitching loss reduction and the drive circuit loss. We have described adesign procedure based on an analytical loss model [16]. By followingthat procedure the peak inductor current may be determined, and then theinductor value may be calculated according to Equation (2).

For the synchronous rectifier MOSFET Q₂, this involves a tradeoffbetween body diode conduction loss and gate drive loss. The body diodeconduction loss may be estimated using Equation (12).

P _(body) _(—) _(Q2) =V _(body) _(—) _(Q2) ·I _(o) ·f _(s) ·t_(body)  (12)

In Equation (12), t_(body) is body diode conduction time and it may beestimated using Equation (13). Equation (13) assumes that the body diodewill conduct during the interval when the gate voltage is between thethreshold and until the gate voltage is large enough so that R_(ds(on))of the synchronous MOSFET is less than about 20 mOhms, which means thevoltage drop across the channel is less than the body diode drop. Thevalues for Q_(gQ2)(V_(20mohm)) and Q_(gQ2)(V_(thQ2)) may be estimatedusing the MOSFET manufacturer datasheet and the body diode conductiontime may be calculated as

$\begin{matrix}{t_{body} = {2\left\lbrack \frac{{Q_{{gQ}\; 2}\left( V_{20\; {mohm}} \right)} - {Q_{{gQ}\; 2}\left( V_{{th}\; Q\; 2} \right)}}{I_{{gQ}\; 2}} \right\rbrack}} & (13)\end{matrix}$

Using P_(Drive) given in Equation (11), and P_(body) _(—) _(Q2) given by(12), the sum of the two loss components may be plotted as P_(optimal)and the optimal gate current, I_(G) _(—) _(Q2) may be determined fromthe graph (at the minimum point of P_(optimal)). For a buck converterand the parameters described below in the Working Example (section 5),the curves are given in FIG. 10. In FIG. 10, the optimal gate current is1.1 A.

3. E. Current-Source Gate Drive Circuit with Integrated Inductor

It is observed from the waveforms of the two inductor currents i_(Lr1)and i_(Lr2) in FIG. 8 that i_(Lr1) is almost a mirror image about thetime axis of i_(Lr2), which has a very good ripple cancellation effectof magnetic flux. This makes it possible to integrate the two inductorsinto one magnetic core.

FIG. 11 shows the magnetic structure of the integrated inductors. It isnoted that the references of the two driver circuits do not need to bethe same. The reduction of components and of complexity resulting fromintegrated inductors is an important factor in multiphase applicationsof VRs such as buck converters. Although FIG. 11 shows this embodimentwith a buck VR, it will of course be appreciated that this embodimentmay be applied to other circuits.

FIG. 12 shows the current-source gate drivers with an integratedinductor. The two inductors (L_(r1) and L_(r2)) are built on the twoouter legs of one E-I core with two air gaps (g₁ and g₂) respectively.The fluxes Φ₁ and Φ₂ in the two outer legs generated by the two windingsbased on the directions of the currents will all flow through the centerleg, which is a low-reluctance magnetic path with no air gap. ThoughL_(r1) and L_(r2) are built on the same E-I core, there is nointeraction between the two flux loops of Φ₁ and Φ₂ and there is nocoupling effect between L_(r1) and L_(r2). Therefore, the principle ofoperation of the current-source driver circuits with the integratedinductor does not change. However, the number of inductor cores isreduced from two to one. Another benefit of using the integratedinductor is that the fluxΦ (Φ=Φ₁+Φ₂) in the center leg has smallerripples owing to the flux ripple cancellation effect of the currenti_(Lr1) and i_(Lr2), as shown in FIG. 13. The smaller flux ripple helpsto reduce the core losses in the center leg at high frequency.

3.F. Example: Current-Source Gate Driver for Control and SynchronousPower Switches of a Synchronous Buck Converter

To verify the functionality of the current-source gate drive circuit,preliminary tests were conducted with a 1 MHz synchronous buckconverter. The specifications were as follows: input voltage V_(in)=12V; output voltage V_(o)=1.5 V; output current I_(o)=30 A; switchingfrequency f_(s)=1 MHz; driver voltage V_(c)=8 V. The PCB was made fromsix-layer 2 oz copper. The components used in the circuit were asfollows:

Control MOSFET Q₁: Si7860DP (30 V N-channel, R_(DS(on))=11 mΩ @V_(GS)=4.5 V, Vishay);

Synchronous MOSFET Q₂: Si7336ADP (30 V N-channel, R_(DS(on))=4 mΩ @(V_(GS)=4.5 V, Vishay);

Output filter inductance: L_(f)=330 nH (R=1.3 mohm, IHLP-5050CE-01,Vishay)

Inductors: L_(r1)=1.0 uH and L₂=1.2 uH

FIG. 14 shows the gate drive signal v_(gs) _(—) _(Q1) (control MOSFET)and v_(gs) _(—) _(Q2) (synchronous MOSFET). The crossover level of thesetwo gate signals is less than the threshold voltage of the switches,such that the dead time is minimized and shoot-through is avoided. It isobserved that v_(gs) _(—) _(Q1) is very smooth and no Miller plateau isobserved as the Miller charge (i.e., the charge in the Miller capacitor)was removed very fast with the constant charging current. Moreover, therise time and fall time of v_(gs) _(—) _(Q1) is less than 15 ns, whichmeans very fast switching speed.

FIGS. 15 and 16 show the inductor current i_(Lr1) and i_(Lr2) with twoinductors and with the integrated inductor, respectively. The observedmirror relationship between i_(Lr1) and i_(Lr2) confirms the feasibilityof inductor integration and lower core loss due to the magnetic fluxcancellation effect. Further, the data confirm that the integratedinductor does not change the principle of operation of thecurrent-source gate drive circuit.

To illustrate the efficiency improvement provided by the current-sourcegate driver, a conventional synchronous buck converter with the sameparameters, using a conventional gate driver, was built. A PredictiveGate Drive UCC 27222 from Texas Instruments was used as the conventionalvoltage-source gate driver.

FIG. 17 shows the measured efficiency comparison for the current-sourcegate driver and the conventional gate driver with an input voltage of 12V and output voltage of 1.5 V. It is observed that at 20 A, theefficiency is improved from 84.0% to 87.3% (an improvement of 3.3%) andat 30 A, the efficiency is improved from 79.4% to 82.8% (an improvementof 3.4%). The data also show that the efficiency of the buck converterwith the current-source gate driver with one integrated inductor wassimilar to that of the buck converter with the current-source gatedriver with two discrete inductors.

FIG. 18 shows the buck converter power loss comparison for thecurrent-source gate driver and the conventional driver. It is noted that30 A load, the current-source gate driver saves approximately 2.2 W (areduction of 23%) compared to the conventional driver. This loss savingsis significant for multiphase VRs. For example, in a five phase VR, thetotal loss savings would be 11 W.

An interesting observation is that if the power loss per phase islimited to 9.5 W, a buck converter with a conventional gate driver canonly provide 26 A output current, while a buck converter withcurrent-source gate driver can provide 30 A (an improvement of 15%). Inother words, if the total output current is 120 A, 5 phases (26 A perphase) of the conventional gate driver are required, whereas only 4phases (30 A per phase) of the current-source gate driver are required.This would yield a significant cost savings and space savings.

FIG. 19 shows the measured efficiency for the current-source gate driverat different output voltages and load currents.

4.A. Hybrid Current-Source Gate Drive Circuit for a Voltage Regulator

In certain applications it might not be cost-effective to implementcurrent-source gate drive circuits for all of the power switchingdevices of a VR. For example, it might be practical to implement onlyone current-source gate drive circuit, for either the control or thesynchronous power switch of a synchronous buck converter. Where only onecurrent-source gate driver is to be used (with a conventional gatedriver being used for the other power switch), the control power switchcurrent-source gate driver may be used, as this driver contributes moreto the overall improvement in efficiency than the synchronous powerswitch current-source gate driver.

FIG. 20 shows a hybrid current-source gate drive circuit for the controlpower switch of a buck converter. The circuit consists of two driveswitches S₁, S₂, an inductor L_(r), a bootstrap capacitor C_(f), and ablocking capacitor C_(b). For the synchronous MOSFET, a conventionalvoltage driver is used, such as, for example, the bipolar totem-poledrive structure shown in FIG. 20, which features low cost andsimplicity. V_(c) is the drive voltage. C_(gs1) and C_(gs2) are theinput gate capacitors of the two power MOSFETs Q₁ and Q₂. Key waveformsare shown in FIG. 21.

FIG. 22 shows the equivalent circuits of the turn-on interval of thecontrol MOSFET. D₁ and D₂ are the body diodes, and C_(ds1) and C_(ds2)are the intrinsic drain-source capacitances of S₁ and S₂, respectively.With reference to FIGS. 21 and 22, operation of the circuit is describedbriefly as follows: In FIG. 22A, during [t₀, t₁], the peak currentI_(Lr) _(—) _(pk) flows through L_(r), C_(f), C_(b) to charge C_(gs1)and C_(ds2) and discharge C_(ds1). C_(gs2) is discharged through the PNPbipolar transistor until Q₂ turns off. The voltage across C_(gs1)increases until at t₁, it is clamped to V_(c) by the body diode D₁ of S₁as seen in FIG. 22B. At the same time, S₁ turns on under zero-voltagecondition. Therefore, there is no switching loss of drive switches S₁and S₂.

4. B. Design Considerations

To achieve design optimization, the loss analysis of the current-sourcegate driver is given. The total power loss of the current-source drivecircuit includes: (1) the resistive loss and the gate drive loss ofswitches S₁ and S₂; (2) the loss of the inductor; and (3) the resistiveloss caused by the internal gate mesh resistance of the control MOSFETs.

The relationship of the peak inductor current and the inductor value isgiven by Equation (14)

$\begin{matrix}{I_{L\; r\; \_ \; p\; k} = \frac{V_{c} \cdot D \cdot \left( {1 - D} \right)}{2{L_{r} \cdot f_{s}}}} & (14)\end{matrix}$

where V_(c) is the gate drive voltage, which may be the input voltage ofthe buck converter; T_(s) is the switching period; L_(r) is the inductorvalue and D is the duty cycle of the control MOSFET Q₁.

As seen from the key waveforms in FIG. 21, the peak current I_(Lr) _(—)_(pk) of the inductor L_(r) is regarded as the current source magnitudeI_(G). So the higher I_(Lr) _(—) _(pk) is, the shorter the switchingtransition is, thus more switching loss can be saved. On the other hand,higher I_(Lr) _(—) _(pk) will result in a larger RMS value of theinductor circulating current i_(Lr) since the waveform of i_(Lr) istriangular, which increases the resistive circulating loss in the drivecircuit and decreases the gate energy recovery efficiency.

Following the optimal design method proposed in [15]-[16], the desireddrive current I_(G) may be obtained and thus the required inductor canbe calculated from Equation (14).

4. C. Example: Hybrid Current-Source Gate Driver for a Synchronous BuckConverter

To verify the performance of the hybrid current-source gate drivecircuit, it was implemented for the control power MOSFET of asynchronous buck converter. The specifications were as follows: inputvoltage V_(in)=12 V; output voltage V_(o)=1.5 V; output current I_(o)=30A; switching frequency f_(s)=1 MHz; driver voltage V_(c)=8 V. The PCBwas constructed from six-layer 2 oz copper. The components used in thecircuit were as follows: Q₁: Si7860DP; Q₂: Si7336ADP; output inductor:L_(f)=330 nH; inductor: L_(r)=1.0 uH.

FIG. 23 shows the gate drive signals v_(gs) _(—) _(Q1) (control MOSFET),v_(gs) _(—) _(Q2) (synchronous MOSFET) and the inductor current i_(Lr).FIG. 24 shows the waveforms for one cycle. It was observed that v_(gs)_(—) _(Q1) was very smooth and no Miller plateau was observed as theMiller charge was removed fast by the constant inductor drive current.Moreover, the rise time and fall time of v_(gs) _(—) _(Q1) was less than15 ns, which results in fast switching speed. The crossover level of thetwo gate signals was less than the threshold voltage of the switches, sothat the dead time was minimized and shoot-through was avoided.

For comparison, a synchronous buck converter with conventional gatedrivers was built. A Predictive Gate Drive UCC 27222 (Texas Instruments)was used as the conventional voltage driver. FIG. 25 shows the measuredefficiency comparison for the current-source gate driver and theconventional gate driver at 1.5 V output. It was observed that at 20 A,the efficiency was improved from 84% to 87% (an improvement of 3.6%) andat 30 A, the efficiency was improved from 79.4% to 82.4% (an improvementof 3.8%). These preliminary experimental results demonstrate theincrease in efficiency provided by the hybrid current-source gate drivecircuit. This circuit requires only one small inductor (typically 400 nHto 800 nH at 1 MHz), thereby achieving low cost, small size, and a lowprofile.

The contents of all cited patents, patent applications, and publicationsare incorporated herein by reference in their entirety.

While the invention has been described with respect to illustrativeembodiments thereof, it will be understood that various changes may bemade to the embodiments without departing from the scope of theinvention. Accordingly, the described embodiments are to be consideredmerely exemplary and the invention is not to be limited thereby.

REFERENCES

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1. A current-source gate drive circuit for use with a switching device having a gate capacitance, comprising: an input terminal for receiving a DC voltage; a first switch connected between the input terminal and an output terminal; a second switch connected between the output terminal and a circuit common; a series circuit comprising a first capacitor and an inductor, the series circuit connected between the input terminal and the output terminal; wherein the gate capacitance of the switching device is connected between the output terminal and the circuit common.
 2. The current-source gate drive circuit of claim 1, further comprising a second capacitor connected between a node between the first capacitor and the inductor, and the circuit common.
 3. The current-source gate drive circuit of claim 2, further comprising a third capacitor connected between the node and the inductor.
 4. The current-source gate drive circuit of claim 1, wherein the circuit common is ground.
 5. The current-source gate drive circuit of claim 1, wherein the switching device is a synchronous power switching device of a buck converter.
 6. The current-source gate drive circuit of claim 1, wherein the switching device is a low side power switching device of a bridge leg.
 7. The current-source gate drive circuit of claim 1, wherein the switching device is a power switching device selected from a MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), and a MCT (MOS controlled thyristor).
 8. A current-source gate drive circuit for use with a switching device having a gate capacitance, comprising: an input terminal for receiving a DC voltage; a rectifier connected between the input terminal and a first node; a first switch connected between the first node and an output terminal; a second switch connected between the output terminal and a floating point; a series circuit comprising a first capacitor and an inductor, the series circuit connected between the first node and the output terminal; and a second capacitor connected between the first node the floating point; wherein the gate capacitance of the switching device is connected between the output terminal and the floating point.
 9. The current-source gate drive circuit of claim 8, wherein the series circuit is connected between the floating point and the output terminal.
 10. The current-source gate drive circuit of claim 8, wherein the switching device is a control power switching device of a buck converter.
 11. The current-source gate drive circuit of claim 8, wherein the switching device is a high side power switching device of a bridge leg.
 12. The current-source gate drive circuit of claim 8, wherein the switching device is a power switching device selected from a MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), and a MCT (MOS controlled thyristor).
 13. A current-source gate drive circuit for use with a switching device having a gate capacitance, comprising: an input terminal for receiving a DC voltage; a rectifier connected between the input terminal and a first node; a first switch connected between the first node and an output terminal; a second switch connected between the output terminal and a floating point; a series circuit comprising a first capacitor and second capacitor, the series circuit connected between the first node and the floating point; and an inductor connected between a point between the first and second capacitors and the output terminal; wherein the gate capacitance of the switching device is connected between the output terminal and the floating point.
 14. The current-source gate drive circuit of claim 13, further comprising a third capacitor connected in series with the inductor, between the first and second capacitors and the output terminal.
 15. The current-source gate drive circuit of claim 13, wherein the switching device is a control power switching device of a buck converter.
 16. The current-source gate drive circuit of claim 13, wherein the switching device is a high side power switching device of a bridge leg.
 17. The current-source gate drive circuit of claim 13, wherein the switching device is a power switching device selected from a MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), and a MCT (MOS controlled thyristor).
 18. A voltage regulator having a high side power switching device and a low side power switching device, each said power switching device having a gate capacitance, comprising: the current-source gate drive circuit of claim 1 for driving the high side power switching device; and the current-source gate drive circuit of claim 7 for driving the low side power switching device.
 19. The voltage regulator of claim 18, wherein the inductor of the current-source gate drive circuit for driving the high side power switching device shares a magnetic component with the inductor of the current-source gate drive circuit for driving the low side power switching device.
 20. A method of controlling switching of a switching device having a gate capacitance, comprising: (a) providing a constant current source in a first direction to charge the gate capacitance of the switching device; (b) clamping the voltage across the gate capacitance to a high value, to turn the switching device on; (c) reversing direction of the constant current source to discharge the gate capacitance of the switching device; and (d) clamping the voltage across the gate capacitance to a low value, to turn the switching device off; wherein the constant current source comprises an inductor current.
 21. The method of claim 20, wherein the switching device is the high side power switching device or the low side power switching device of a voltage regulator or a bridge leg.
 22. A method of controlling independently the switching of high side and low side power switching devices of a voltage regulator, each said power switching device having a gate capacitance, comprising: independently applying the method of claim 20 to each of the high side and low side power switching devices of the voltage regulator.
 23. The method of claim 22, wherein inductor currents applied to the high side and low side power switching devices are not equal.
 24. The method of claim 22, further comprising: applying the method of claim 20 to the high side power switching device of the voltage regulator using a high inductor current; and applying the method of claim 20 to the low side power switching device of the voltage regulator using a low inductor current.
 25. The method of claim 22, wherein the voltage regulator is a buck converter.
 26. The method of claim 20, wherein controlling includes repeating steps (a) to (d) once per cycle at a frequency of at least 300 kHz.
 27. The method of claim 26, wherein the frequency is at least 1 MHz. 